1. Field of the Invention
The present invention relates to a package-on-package (POP) semiconductor device, in which a semiconductor package is stacked on another semiconductor package and each of the semiconductor packages includes an internal semiconductor chip, a semiconductor package included in the POP semiconductor device, and methods of manufacturing them.
2. Description of the Related Art
There are various suggestions on POP semiconductor devices and semiconductor packages included in the POP semiconductor devices, for example, in Japanese Patent Kokai Publication No. 2008-16729 (Patent Document 1) and “Sanjigen jissou no PoP ni shin kouzou, teihaika to sekisoujiyuudo koujou wo jitsugen (a new structure of three-dimensional PoP which realizes to reduce package height and improve stacking flexibility)”, Nikkei Electronics of Jun. 16, 2008, pp. 12-13 (Non-Patent Document 1).
Patent Document 1 (see FIG. 1 and claim 1, for example) describes a double-sided electrode structure which is a semiconductor package internally having a semiconductor chip. The double-sided electrode structure includes an organic substrate, on which the semiconductor chip is mounted, an electrode which is formed on a lower surface of the organic substrate, a sealing resin which covers the semiconductor chip, pillar-shaped electrodes for internal connection which are connected with a wiring on an upper surface of the organic substrate and penetrates the sealing resin, and a redistribution layer which is formed on an upper surface of the sealing resin.
Further, Patent Document 1 (see FIGS. 1 to 6 and claim 14, for example) describes a method of manufacturing the double-sided electrode structure. In this manufacturing method, the semiconductor chip is mounted on the upper surface of the organic substrate which has the electrodes for external connection on the lower surface thereof, each end of the plurality of pillar-shaped electrodes for internal connection which are united as a single unit by a uniting plate are connected with the upper surface of the organic substrate, the semiconductor chip is resin-sealed, then the uniting plate is removed by polishing or grinding, thereby the united plurality of electrodes for internal connection are divided into individual electrodes for internal connection and the divided electrodes are used as electrodes for external connection on an upper surface.
Non-Patent Document 1 (see FIG. 1, FIG. 3 and an explanation thereof, for example) describes a double-sided electrode package which is a semiconductor package internally having a semiconductor chip. The double-sided electrode package includes an interposer on which the semiconductor chip is mounted, a solder ball which is provided on a lower surface of the interposer, a sealing resin which covers the semiconductor chip, a pillar-shaped via which penetrates the sealing resin, and a redistribution layer which is formed on an upper surface of the sealing resin.
Non-Patent Document 1 (see FIG. 3 and an explanation thereof, for example) also describes a method of manufacturing the double-sided electrode package. In this manufacturing method, the semiconductor chip is mounted on the interposer, the pillar-shaped vias are formed on a supporting plate of stainless steel by electroplating, the vias which are supported on the supporting plate are connected on the interposer, the sealing resin is filled on the semiconductor chip, the supported vias are divided into a plurality of individual vias by removing the supporting plate, and upper ends of the individual vias are used as electrodes on an upper surface.
However, in the device of Patent Document 1, the electrodes for internal connection are the pillar-shaped electrodes which are united with the uniting plate, and a time-consuming process is required such that each of the terminals of the pillar-shaped electrodes are connected with a wiring pattern on the organic substrate and then the uniting plate is removed by polishing or grinding. Thus, the device has the following problems that: it is difficult to reduce manufacturing costs and manufacturing time (i.e., to reduce a turnaround time (TAT)), and consequently, it is difficult to lower a price of a product.
On the other hand, the device of Non-Patent Document 1 has the vias which are the pillar-shaped electrodes formed by electroplating on the supporting plate of stainless steel. Thus, the device has the following problems that: it is difficult to reduce manufacturing costs because photomasks are used in photolithography technology for forming a resistor pattern for the electroplating, it is also difficult to reduce manufacturing time (i.e., to reduce a TAT) because it takes a long time to form the vias by electroplating, and consequently, it is difficult to lower a price of a product.